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Structure versus schematic (LVS) comparability is a vital step in built-in circuit (IC) design verification, making certain that the bodily format of the circuit matches its schematic illustration. The first purpose of LVS is to confirm the correctness and performance of the design. Historically, LVS comparability is carried out throughout signoff verification, the place devoted instruments examine format and schematic knowledge to determine any inconsistencies or errors. Nonetheless, uncovering errors on the signoff stage results in time-consuming iterations that delay design closure and time to market. Whereas early-stage LVS comparability might mitigate these points, it usually generates thousands and thousands of error outcomes as a result of incomplete standing of the design.

The Calibre nmLVS™ Recon Evaluate resolution introduces an clever shift-left course of for quick and exact LVS comparability earlier within the design cycle. It automates the black boxing of incomplete blocks and facilitates computerized port mapping, permitting designers to realize sooner LVS iterations on early-stage designs.

Challenges of conventional LVS verification

Within the conventional LVS verification course of, designers should confirm the format in opposition to its schematic illustration to make sure that the ultimate product features as supposed. As a result of all design blocks should be accomplished and prepared for ultimate comparability, verification groups wait till signoff phases to carry out thorough checks. Any errors found throughout this late-stage LVS run can set off further verification iterations, resulting in wasted time and sources. Designers are then caught in a cycle of re-running the LVS course of every time a repair or replace is applied, leading to a bottleneck throughout signoff.

Designers might run LVS examine earlier, though within the early phases of design many blocks should not but finalized, making a complete LVS comparability impractical. Operating LVS on incomplete designs can generate thousands and thousands of error messages, a lot of which aren’t actionable as a result of they originate from the uncompleted parts of the format. This overwhelming variety of outcomes makes it tough to pinpoint precise design points, rendering conventional LVS strategies impractical for early-stage verification.

As proven in determine 1, the verification circulate could be extra advanced when design blocks are accomplished at totally different occasions, driving a number of iterations of verification checks as every block is built-in into the general format.

Fig. 1: Design verification cycle with blocks at totally different ranges of completion.

Shifting left for early LVS verification

Implementing a shift-left methodology for LVS verification means performing format vs. schematic comparisons earlier within the design cycle, earlier than all blocks are finalized. To allow this, the circulate should help flexibility in coping with incomplete designs and permit for extra focused verification of important blocks and connections.

One technique to obtain that is by way of automation strategies like black boxing and port mapping. By abstracting the interior particulars of incomplete blocks whereas preserving their exterior connectivity data, the verification circulate could be tailor-made to concentrate on interactions between accomplished and incomplete sections of the design. Automated port mapping, however, ensures that every one exterior connections between format and schematic are appropriately aligned for correct early-stage comparisons.

A brand new method to early LVS verification

A complicated methodology for early-stage LVS verification leverages these automated processes to speed up the shift-left verification course of. For example, clever black boxing of incomplete blocks can considerably scale back the variety of error outcomes generated, making it simpler for verification groups to determine precise connectivity points between blocks.

The shift-left circulate additionally advantages from using a strong comparability engine that may analyze format and schematic knowledge shortly and effectively, skipping pointless operations and calculations. This method focuses on the toughest issues early within the circulate, leading to fewer errors found on the signoff stage and finally rushing up design closure.

The flows illustrated in determine 2 exhibits how this shift-left methodology streamlines the verification course of by lowering pointless steps and specializing in important design points.

Fig. 2: The standard full LVS circulate with all steps (left) vs. the Calibre nmLVS Recon circulate (proper).

Benefits of early LVS examine

Adopting a shift-left methodology for LVS verification gives a number of key advantages to semiconductor design groups:

Early detection of errors: By performing LVS comparisons earlier within the design circulate, errors could be recognized and resolved earlier than they change into deeply embedded within the design. This proactive method reduces the chance of pricey rework and minimizes the variety of iterations wanted throughout signoff.

Accelerated design verification: Automating the comparability course of streamlines design verification, permitting designers to determine and resolve points effectively, even when all blocks should not finalized. This results in sooner general circuit verification and reduces the effort and time required for guide inspection.

Improved collaboration and debugging: With a centralized platform for verifying design correctness and sharing suggestions, early-stage LVS verification promotes collaboration throughout design groups. Engineers can isolate points extra successfully and supply insights to their colleagues, enhancing general design high quality.

Elevated design confidence: Guaranteeing alignment between format and schematic representations from the early phases of design boosts confidence within the ultimate product’s correctness. By the point the design reaches signoff, many of the important connectivity points have already been resolved.

Actual-world functions

Calibre nmLVS Recon has demonstrated important advantages in actual design tasks, together with 10x runtime enhancements and 3x decrease reminiscence necessities. A verification crew at Marvell, for instance, enhanced their LVS circulate over the complete design cycle utilizing Calibre nmLVS SI, attaining sooner verification occasions and improved effectivity.

Conclusion

Shifting LVS examine duties earlier into the design circulate gives important advantages to IC design groups. Our novel method to early top-level LVS comparability automates black boxing and port mapping so designers can carry out complete verification even when all blocks should not finalized. This accelerates design verification, improves collaboration, and enhances design confidence in semiconductor design workflows.

Be taught extra by downloading my current technical paper “Speed up design verification with Calibre nmLVS Recon Evaluate.”